SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs

Stencil computation is one of the fundamental computing patterns in many application domains such as scientific and image processing. While there are promising studies that accelerate stencils on FPGAs, lacks an automated acceleration framework to systematically explore both spatial temporal parallelisms for iterative could be either computation-bound or memory-bound. In this article, we present SASA, a scalable automatic stencil modern HBM-based FPGAs. SASA takes high-level DSL FPGA platform inputs, automatically exploits best parallelism configuration based our accurate analytical model, generates optimized design with TAPA synthesis C++ well its corresponding host code. Compared state-of-the-art SODA only parallelism, achieves average speedup 3.41× up 15.73× Xilinx Alveo U280 board wide range kernels.